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| FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability August 2009 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator with Synchronization Capability Features Single-Supply Operation with 6A Output Current Over 94% Efficiency Fully Synchronous Operation with Integrated Schottky Diode on Low-Side MOSFET Boosts Efficiency Single Supply Device for VIN > 6.5V - 24V Programmable Frequency Operation (200-600KHz) Externally Synchronizable Clock with Master/Slave Provisions Wide Input Range with Dual Supply: 3.0V to 24V Output Voltage Range: 0.8V to 80%VIN Power-Good Signal Accepts Ceramic Capacitors on Output External Compensation for Flexible Design Starts Up on Pre-Bias Outputs Integrated Bootstrap Diode Programmable Over-Current Protection Under-Voltage, Over-Voltage, and ThermalShutdown Protections 5x6mm, 25-pin, 3-pad MLP Description The FAN210SV06 TinyBuck is a highly efficient, small-footprint, programmable-frequency, 6A integrated synchronous buck regulator. FAN21SV06 contains both synchronous MOSFETs and a controller/driver with optimized interconnects in one package, which enables designers to solve high-current requirements in a small area with minimal external components, thereby saving cost. On-board internal 5V regulator enables single-supply operation for input voltages >6.5V. The FAN21SV06 can be configured to drive multiple slave devices OR synchronize to an external system clock. In slave mode, FAN21SV06 may be set up to be free-running in the absence of a master clock signal. External compensation, programmable switching frequency, and current-limit features allow for design optimization and flexibility. High-frequency operation allows for all ceramic solutions. Fairchild's advanced BiCMOS power process combined with low-RDS(ON) internal MOSFETs and a thermally efficient MLP package provide the ability to dissipate high power in a small package. Integration helps to minimize critical inductances making layout simpler and more efficient compared to discrete solutions. Output over-voltage, under-voltage, over-current and thermal-shutdown protections help protect the device from damage during fault conditions. FAN21SV06 prevents pre-biased output discharge during startup in point-of-load applications. AN-6033 -- FAN21SV06 Design Guide - AN-8022 -- TinyCalcTM Calculator TM Applications Servers & Telecom Graphics Cards & Displays High-End Computing Systems Set-Top Boxes & Game Consoles Point-of-Load Regulation Ordering Information Part Number FAN21SV06MPX FAN21SV06EMPX Operating Eco Temperature Range Status -10C to 85C -40C to 85C RoHS RoHS Package Packing Method Molded Leadless Package (MLP) 5x6mm Tape and Reel Molded Leadless Package (MLP) 5x6mm Tape and Reel For Fairchild's definition of please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Typical Application Diagram Figure 1. Typical Application, Master, VIN=6.5V to 24V Block Diagram Figure 2. Block Diagram (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 Reg www.fairchildsemi.com 2 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Pin Configuration Figure 3. MLP 5x6mm Pin Configuration (Bottom View) Pad / Pin Definitions Pad / Pin P1, 6-12 P2, 3-5 P3, 21-23 1 2 13 Name SW VIN PGND BOOT VIN_Reg PGOOD Description Switching Node. Junction of high-side and low-side MOSFETs. Power Input Voltage. Supply voltage for the converter. Power Ground. Power return and Q2 source. High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an internal synchronous bootstrap diode to recharge the capacitor on this pin to 5V. Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage >6.5V with 1F bypass capacitor at the pin. Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is outside the limits specified in the electrical specs. PGOOD does not assert HIGH until the fault latch is enabled. ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the regulator after a latched-fault condition. This input has an internal pull-up. When a latched fault occurs, EN is discharged by a current sink. 5V Regulator Output. Internal regulator output that provides power for the IC's logic and analog circuitry. This pin should be connected to AGND through a >2.2f X5R/X7R capacitor. Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection. Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the internal default setting. Oscillator Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the oscillator frequency and configures the CLK pin as an output (master). Tying this pin to 5V_Reg through a resistor configures the CLK signal as an input (slave) and establishes the free-running oscillator frequency. Output Voltage Feedback. Connect through a resistor divider to the output voltage. Compensation. Error amplifier output. Connect the external compensation network between this pin and FB. Clock. Bi-directional signal pin, depending on master/slave configuration. When configured as a master, this pin represents the clock output that connects directly to the slave(s) for synchronizing with 180 phase shift. Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp amplitude and also provides voltage feedforward functionality. 14 EN 15 16 17 5V_Reg AGND ILIM 18 19 20 24 25 RT FB COMP CLK RAMP (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 3 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VIN, VIN_Reg to AGND 5V_Reg to AGND BOOT to PGND BOOT to SW SW to PGND All other pins ESD Continuous AGND=PGND AGND=PGND Conditions Min. Max. 28 6 35 Units V V V V V V V kV -0.5 -0.5 -5 -0.3 Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 1.5 2.5 Transient (t < 20ns, f < 600KHz) 6.0 24.0 30 6.0 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol fSW VIN, VIN_Reg TA TJ Parameter Switching Frequency Supply Voltage for Power and Bias Ambient Temperature Junction Temperature Conditions VIN to PGND VIN_Reg to AGND FAN21SV06MX FAN21SV06EMX Min. 200 3.0 6.5 -10 -40 Typ. 500 Max Units 600 24.0 24.0 +85 +85 +125 KHz V V C C C Thermal Information Symbol TSTG TL JC J-PCB PD Storage Temperature Lead Soldering Temperature, 30sec P1 (Q2) Thermal Resistance: Junction-to-Case P2 (Q1) P3 Thermal Resistance: Junction-to-Mounting Surface Total Power Dissipation in the package, TA=25C (1) (1) Parameter Min. -65 Typ. Max. +150 +300 Units C C C/W C/W C/W C/W 4 7 4 35 (1) 2.8 W Note: 1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 37. Actual results are dependent upon mounting method and surface related to the design. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 4 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Electrical Characteristics Recommended operating conditions and using the circuit shown in Figure 1, with VIN, VIN_Reg=12V, unless otherwise noted. Parameter Power Supplies Operating Current (VIN+VIN_Reg) VIN_Reg Operating Current VIN_Reg Quiescent Current VIN_Reg Standby Current 5V_Reg Output Voltage 5V_Reg Max Current Load VIN_Reg UVLO Threshold Reference Reference Voltage measured at FB (See Figure 4 for Temperature Coefficient) Oscillator Frequency Frequency in Slave Mode compared to Master Mode Minimum On-Time Duty Cycle Ramp Amplitude, (2) Peak-to-Peak (2) Minimum Off-Time Synchronization CLK Output Pulse Width CLK Output Sink Current CLK Output Source Current CLK Input Pulse Width CLK Input Source Current CLK Input Threshold, Rising Soft-Start VOUT to Regulation (T0.8) Fault Enable/SSOK (T1.0) Error Amplifier (2) DC Gain (2) Gain Bandwidth Product Output Voltage Swing (VCOMP) Output Current, Sourcing Output Current, Sinking FB Bias Current (2) Conditions VIN=12V, 5V_Reg open, CLK open, fSW =500KHz, No Load EN=High, 5V_Reg open, CLK open, fSW =500KHz EN=High, FB=0.9V EN=0, VIN=12V Internal VCC Regulator, No Load (6.5V Min. Typ. 22 11 4 Max. 30 Units mA mA 4.7 5.0 5 1 5.3 5 mA mA V mA V V mV mV KHz KHz % ns % V 5.6 6.3 5 806 805 345 660 +15 794 795 255 540 -15 800 800 300 600 40 80 0.5 100 65 85 150 100 0.35 -2.0 -170 1.93 ns ns mA mA ns A V ms ms dB MHz V mA mA nA Master (RT to GND) Master, VCLK=0.4V Master, VCLK=2V Slave: VCLK > 2V Slave: VCLK=1V Slave 70 0.25 -2.5 50 -230 1.73 85 -200 1.83 2.5 3.1 Frequency=500KHz VIN_Reg > 6.5V 5V_Reg=5V, VCOMP=2.2V 5V_Reg=5V, VCOMP=1.2V VFB=0.8V, 25C 80 12 0.4 1.5 0.8 -850 85 15 2.2 1.2 -650 4.0 2.5 1.5 -450 Note: 2. Specifications guaranteed by design and characterization; not production tested. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 5 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Electrical Characteristics (Continued) Recommended operating conditions and using the circuit shown in Figure 1 with VIN, VIN_Reg=12V, unless otherwise noted. Parameter Control Functions EN Threshold, Rising EN Hysteresis EN Pull-Up Current EN Discharge Current FB OK Drive Resistance PGOOD LOW Threshold PGOOD Low Voltage PGOOD Leakage Current Protection and Shutdown Current Limit Conditions Min. Typ. 1.35 250 -6 1 800 -11.0 +10.0 0.2 Max. 2.00 -4 1000 -8.0 +13.5 0.4 1.0 Units V mV A A K %VREF %VREF V A VIN_Reg >6.5V Auto-Restart Mode, VIN_Reg>6.5V FB < VREF, 2 Consecutive Clock Cycles (3) FB > VREF, 2 Consecutive Clock Cycles IOUT < 2mA VPGOOD=5V RILIM open, fsw=500KHz,, VOUT=1.8V, Rramp=200k, 16 Consecutive Clock (3) Cycles VIN_Reg > 6.5V, 25C (3) -8 -14.5 +6.5 7 -11 9 -10 155 30 115 73 250 250 11 -9 A A C C %VOUT %VOUT mV mV ILIM Current Over-Temperature Shutdown Internal Temperature Over-Temperature Hysteresis (3) Over-Voltage Threshold 2 Consecutive Clock Cycles (3) Under-Voltage Shutdown 16 Consecutive Clock Cycles Fault-Discharge Threshold Measured at FB pin Fault-Discharge Hysteresis Measured at FB pin (VFB ~500mV) 110 68 120 78 Note: 3. Delay times are not tested in production. Guaranteed by design. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 6 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Typical Characteristics 1.010 1.005 V FB 1.000 0.995 0.990 -50 0 50 Temperature (oC) 100 150 1.20 1.10 I FB 1.00 0.90 0.80 -50 0 50 Temperature (oC) 100 150 Figure 4. Reference Voltage (VFB) vs. Temperature, Normalized Figure 5. Reference Bias Current (IFB) vs. Temperature, Normalized 1500 1200 900 600 300 0 0 20 40 60 80 100 120 140 RT (K) 1.02 1.01 Frequency Frequency (KHz) 600KHz 1.00 300KHz 0.99 0.98 -50 0 50 Temperature ( C) o 100 150 Figure 6. Frequency vs. RT (Master) Figure 7. Frequency vs. Temperature, Normalized 1.60 1.40 I ILIM 1.04 1.02 1.00 0.98 0.96 RDS 1.20 1.00 0.80 0.60 -50 0 50 Temperature ( C) o Q1 ~0.32 %/ C Q2 ~0.35 %/ C 100 150 o o -50 0 50 Temperature ( C) o 100 150 Figure 8. RDS vs. Temperature, Normalized (5V_Reg=VGS=5V) Figure 9. ILIM Current (IILIM) vs. Temperature, Normalized (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 7 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Application Circuit Figure 10. Single-Supply Application Circuit: 1.8VOUT, 500KHz, Master Figure 11. Dual-Supply Application Circuit : 1.2VOUT, 600KHz, Master 3.3V - 8V Input (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 8 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Typical Performance Characteristics Typical operating characteristics using the circuit shown in Figure 1, unless otherwise specified. 95 95 1.8V_Eff 8-24V_300Khz 3.3V_Eff 8-24V_300Khz 90 Efficiency (%) 90 Efficiency (%) 85 85 80 8V 75 12V 16V 20V 24V 70 0 1 2 3 Load (A) 80 8V 12V 16V 20V 24V 75 70 0 1 2 3 Load (A) 4 5 6 4 5 6 Figure 12. 0.2 1.8 VOUT Efficiency Over VIN vs. Load Figure 13. 3.3 VOUT Efficiency vs. Load (Circuit Value Changes) 0.15 Load Regulation % Change in ouput voltage as compared to set value at 0 Amps 0.1 0.05 0 0 -0.05 -0.1 -0.15 -0.2 12V Input 16V Input Line Regulation 0.15 % Change in ouput voltage as com pared to set value at 6.5V 0.1 0.05 0 0 -0.05 -0.1 -0.15 -0.2 Input Voltage (V) 5 10 15 20 No Load 0.5A 1 2 3 4 5 6 7 25 Load (A) Figure 14. 1.8 VOUT Line Regulation 90 80 70 Temperature (Deg C) 60 50 40 30 20 10 0 1 2 3 Load (A) 4 5 6 12Vin_HS 12Vin_LS 24Vin_HS 24Vin_LS Figure 15. 1.8 VOUT Load Regulation 90 Peak CaseTempr over Mosfet Location @ Room Tempr - 5V Output, 300Khz Peak CaseTempr over Mosfet Location @ Room Tempr - 3.3V Output, 500Khz 80 70 Temperature (Deg C) 60 50 40 30 20 10 0 1 2 3 14V_HS 14V_LS 4 Load (A) 5 6 Figure 16. Peak Case Temp over MOSFET Locations 3.3V Output, 12V and 24V Input (500KHz) Figure 17. Peak Case Temp. Over MOSFET Locations 5V Output (300KHz) (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 9 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Typical Performance Characteristics (Continued) Typical operating characteristics using the circuit shown in Figure 1. VIN=12V, unless otherwise specified. VOUT EN VOUT CLK IOUT PGood Figure 18. CLK and VOUT at Startup Figure 19. Transient Response, 3-6A Load VOUT EN SW SW Figure 20. Startup on Pre-Bias Figure 21. Restart on Fault VOUT CLK CLK EN PGood SW Figure 22. Shutdown, 1A Load Figure 23. Slave (500KHz Free-Run to 600KHz Synchronization) (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 10 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Typical Performance Characteristics (Continued) Typical operating characteristics using the circuit shown in Figure 1, unless otherwise specified. 95 95 1.8V_Eff 8-24V_600Khz 90 90 Efficiency (%) Efficiency (%) 85 85 3.3V_Eff 8-24V_600Khz 80 8V 12V 16V 20V 24V 80 8V 75 12V 16V 20V 24V 75 70 0 1 2 3 Load (A) 4 5 6 70 0 1 2 3 Load (A) 4 5 6 Figure 24. 1.8 VOUT Efficiency 600KHz 3 Figure 25. 3.3 VOUT Efficiency 600KHz 95 2.5 5V_PWRLOSS_12-24V_300Khz 90 Efficiency (%) Power Loss (W) 5V_Eff12-24V_300Khz 85 2 Using DR1050-2R2-R Inductor from Cooper 1.5 Using DR1050-2R2-R Inductor from Cooper 80 12V 16V 20V 24V 1 12V 0.5 16V 20V 24V 0 0 1 2 3 Load (A) 4 5 6 75 70 0 1 2 3 Load (A) 4 5 6 Figure 26. 5 VOUT Efficiency 300KHz (Circuit Values Change) 95 Figure 27. Device Power Loss (5 VOUT, 300KHz) (Circuit Values Change) 7 1.8V_Eff, 12V Input 90 6 5 Vout Vs Load Current Input Voltage = 20V Temperature rise = 80DegC Efficiency (%) 85 Load Current (A) 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Vout (V) 80 300Khz 75 400Khz 500Khz 600Khz 70 0 1 2 3 Load (A) 20Vin_500Khz 20Vin_600Khz 4 5 6 Figure 28. 1.8 VOUT Efficiency Over fSW (Circuit Values Change) Figure 29. Typical Output Operating Area Based on Thermal Limitations (Circuit Values Change) (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 11 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Circuit Operation PWM Generation Refer to Figure 2 for the PWM control mechanism. FAN21SV06 uses the summing-mode method of control to generate the PWM pulses. An amplified currentsense signal is summed with an internally generated ramp and the combined signal is compared with the output of the error amplifier to generate the pulse width to drive the high-side MOSFET. Sensed current from the previous cycle is used to modulate the output of the summing block. The output of the summing block is also compared against a voltage threshold set by the RLIM resistor to limit the inductor current on a cycle-bycycle basis. The controller facilitates external compensation for enhanced flexibility. Soft-Start FAN21SV06 uses an internal digital soft-start circuit to slowly ramp up the output voltage and limit inrush current during startup. When 5V_Reg is in regulation and EN is high, the circuit releases SS and enables the PWM regulator. Soft-start time is a function of switching frequency (number of clock cycles). Once internal SS ramp has charged to 0.8V (T0.8), the output voltage is in regulation. Until SS ramp reaches 1.0V (T1.0), only over-current-protection circuit is active during soft-start and all other output protections are inhibited. In dual-supply operation mode, it is necessary to apply VIN before VIN_Reg reaches its UVLO threshold to avoid skipping the soft-start cycle. Initialization Once VIN_Reg voltage exceeds the UVLO threshold and EN is HIGH, the IC checks for an open or shorted FB pin before releasing the internal soft-start ramp (SS). If R1 is open (Figure 1), error amplifier output (COMP) is forced LOW and no pulses are generated. After the SS ramp times out (T1.0), an under-voltage fault occurs. If the parallel combination of R1 and RBIAS is 1k, the internal SS ramp is not released and the regulator does not start. Internal Regulator FAN21SV06 facilitates single-supply operation for input voltages >6.5V. At startup, the output of the internal regulator tracks the input voltage and comes into regulation (5V) when VIN_Reg exceeds the UVLO threshold. The EN pin is released at the same time. The output voltage of the internal regulator (5V_Reg) is set to 5V. The internal regulator supplies power to all the control circuits including the drivers. For applications with VIN<6.5V, FAN21SV06 can be used if VIN_Reg is provided with a separate low-power source >6.5V. VIN_Reg supply should come up after VIN during dual-supply operation. The VIN_Reg pin should always be decoupled with at least 1F ceramic capacitor (see Figure 11). Since VCC is used to drive the internal MOSFET gates, high peak currents are present on the 5V_Reg pin. Connect a >2.2f X5R or X7R decoupling capacitor between the 5V_Reg pin and PGND. In addition to supplying power for the control circuits internally, 5V_Reg output can be used as a reference voltage for other applications requiring low noise reference voltage. 5V_Reg is capable of sourcing up to 5mA of output current. When EN is pulled LOW externally, 5V_Reg output is still present but the IC is in standby mode with no switching. Figure 30. Typical Soft-Start Timing Diagram VIN_Reg UVLO or toggling the EN pin discharges the SS and resets the IC. Startup on Pre-Bias The regulator does not allow the low-side MOSFET to operate in full synchronous mode until SS reaches 95% of VREF (~0.76V). This enables the regulator to startup on a pre-biased output and ensures that output is not discharged during the soft-start cycle. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 12 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Protections The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, and under-voltage conditions. Under-Voltage Protection If FB remains below the under-voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. This fault is prevented from setting the fault latch during soft-start. Figure 31. Enable Control with Latch Option Over-Voltage Protection If FB exceeds 115% * VREF for two consecutive clock cycles, the fault latch is set and shutdown occurs. A shorted high-side MOSFET condition is detected when SW voltage exceeds ~0.7V while the low-side MOSFET is fully enhanced. The fault latch is set immediately upon detection. These two fault conditions are allowed to set the fault latch at any time, including during soft-start. Power Good (PGOOD) Signal PGOOD is an open-drain output that asserts LOW when VOUT is out of regulation, as measured at the FB pin. The thresholds are specified in the Electrical Specifications section. PGOOD does not assert HIGH until soft start is complete (T1.0). Application Information Setting the Output Voltage The output voltage of the regulator can be set from 0.8V to ~80% of VIN by an external resistor divider (R1 and RBIAS in Figure 1). For output voltages >3.3V, output current rating may need to be de-rated depending on the ambient temperature, power dissipated in the package and the PCB layout. (Refer to Thermal Information table and Figure 29.) The internal reference is set to 0.8V with 650nA sourced from the FB pin to ensure that the regulator does not start if the pin is left open. The external resistor divider is calculated using: V - 0 .8 V 0 .8 V = OUT + 650nA R BIAS R1 Over-Temperature Protection The chip incorporates an over-temperature-protection circuit that sets the fault latch when a die temperature of about 155C is reached. The IC is allowed to restart when the die temperature falls below 125C. EN / Auto-Restart After a fault, EN pin is discharged with 1A current pull down to a 1.1V threshold before the internal 800k pull up is restored. A new soft-start cycle begins when EN charges above 1.35V. Depending on the external circuit, the FAN21SV06 can be configured to remain latched off or automatically restart after a fault, as listed in Table 1. Table 1. Fault / Restart Configurations EN pin Pull to GND Connected to 5V_Reg Open Cap to GND Controller / Restart State Standby No restart - latched OFF Immediate restart after fault New soft-start cycle after: EN is HIGH (Auto Restart Mode) (1) Connect RBIAS between FB and AGND. Setting the Clock Frequency Oscillator frequency is determined by a resistor, RT, that is connected between the (RT)pin and AGND (Master Mode) or 5V_Reg (Slave Mode): f( KHz ) = 10 6 ( 65 * RT ) + 135 (2) where RT is expressed in k. RT ( K ) = (106 / f ) - 135 65 With EN left open, restart is immediate. If auto-restart is not desired, tie the EN pin high with a logic gate to keep the 1A current sink from discharging EN to 1.1V. Figure 31 shows one method to pull up EN to VCC for a latch configuration. (3) where frequency (f) is expressed in KHz. In slave mode, the switching frequency is about 10% slower for the same RT. The regulator does not start if RT is open in Master mode. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 13 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Calculating the Inductor Value Typically the inductor value is chosen based on ripple current (IL) which is chosen between 10 to 35% of the maximum DC load. Regulator designs that require fast transient response use a higher ripple-current setting while regulator designs that require higher efficiency keep ripple current on the low side and operate at a lower switching frequency. IL = VOUT * (1 - D) L*f RILIM (K ) = 95 + 5 * IOUT * KT * K 1 + VOUT * 3.33 * 106 RRAMP * fSW (7) (4) where: I=desired current-limit set point in Amps, KT=the normalized temperature coefficient of the low-side MOSFET (Q2) from Figure 8. K1=Overload co-efficient (use 1.2 to 1.4) VOUT=Set output voltage RRAMP=Ramp resistor used, in k fSW =Selected switching frequency, in KHz. After 16 consecutive pulse-by-pulse current-limit cycles, the fault latch is set and the regulator shuts down. Cycling VIN_Reg or EN restores operation after a normal soft-start cycle (refer to Auto-Restart section). The over-current protection fault latch is active during the soft-start cycle. Use a 1% resistor for RILIM. For a given RRAMP and RILIM setting, the current-limit point varies slightly in an inverse relationship to VIN. In case RILIM is not connected, the IC uses the internal default current-limit threshold. where f is the oscillator frequency, and L= VOUT * (1 - D) IL * f (5) Setting the Ramp-Resistor Value As a starting point, set the internal ramp amplitude (VRAMP) to 0.5V. RRAMP is approximately: RRAMP (K ) = 18 x10 - 6 * VIN * f (VIN - 1.8 ) * VOUT -2 (6) Loop Compensation The control loop is compensated using a feedback network around the error amplifier. Figure 33 shows a complete Type-3 compensation network. Type-2 compensation eliminates R3 and C3. COMP C2 C1 R2 R1 R3 C3 R3 RBIAS VREF FB where frequency (f) is expressed in KHz. Setting the Current Limit There are two levels of current-limit thresholds in FAN21SV06. The first level of protection is through an internal default limit set at the factory to provide cycle- by-cycle current limit and prevent output current beyond normal usage levels. The second level of protection is a flexible one to be set externally by the user. Currentlimit protection is enabled whenever the lower of the two thresholds is reached. The FAN21SV06 uses its internal low-side MOSFET as the current-sensing element. The current-limit threshold voltage (VILIM) is compared to the voltage drop across the low-side MOSFET, sampled at the end of each PWM offtime/cycle. The internal default threshold (ILIM open) is temperature compensated. VOUT Figure 33. Compensation Network Since the FAN21SV06 employs summing current-mode architecture, Type-2 compensation can be used for many applications. For applications that require wide loop bandwidth and/or use very low-ESR output capacitors, Type-3 compensation may be required. RRAMP provides feedforward compensation for changes in VIN. With a fixed RRAMP value, the modulator gain increases as VIN is reduced, which could make it difficult to compensate the loop. For low-input-voltage-range designs (3V to 8V), RRAMP and the compensation component values are going to be different as compared to designs with VIN between 8V and 24V. Figure 32. ILIM Network The 10A current sourced from the ILIM pin can be used to establish a lower, temperature-dependent, current-limit threshold by connecting an external resistor (RILIM) to AGND: (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 14 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Master/Slave Configuration When first enabled, the IC determines if it is configured as a master or slave for synchronization, depending on how RT is connected. Table 2. Master / Slave Configuration RT to: GND 5V_Reg Master / Slave Master Slave, free-running CLK Pin Output Input Figure 35. Slave-CLK-Input Block Diagram One or more slaves can be connected directly to a o master or system clock to achieve a 180 phase shift. Slaves free-run in the absence of an external clock signal input when RT is connected to 5V_Reg, allowing regulation to be maintained. It is not recommended to leave RT open when running in slave mode to avoid noise pick up on the clock pin. Slave free-running frequency should be set at least 25% lower than the incoming synchronizing pulse frequency. Maximum synchronizing clock frequency is recommended to be below 600KHz. Figure 36. Slaves with 180 Phase Shift o Synchronization The synchronization method employed by the FAN21SV06 also provides the following features for maximum flexibility. Synchronization to an external system clock Multiple FAN21SV06s can be synchronized to a single master or system clock Independently programmable phase adjustment for one or multiple slaves Free-running capability in the absence of system clock or, if the master is disabled/faulted, the slaves can continue to regulate at a lower frequency The FAN21SV06 master outputs an 85ns-wide clock o (CLK) signal, delayed 180 from its leading PWM edge. This feature allows out-of-phase operation for the slaves, thereby reducing the input capacitance requirements when more than one converter is operating on the same input supply. The leading SW-node edge is delayed ~40ns from the rising PWM signal. On a slave, synchronization is rising-edge triggered. The CLK input pin has a 1.8V threshold and a 200A current source pull-up. In Master mode, the clock signals go out after powergood signal asserts high. Likewise, in Slave mode synchronization to an external clock signal occurs after the power-good signal goes high. Until then, the converter operates in free-run mode. Since the synchronizing circuit utilizes a narrow reset o pulse, the actual phase delay is slightly more than 180 . The FAN21SV06 is not intended for use in singleoutput, multi-phase regulator applications. PCB Layout Good PCB layout and careful attention to temperature rise is essential for reliable operation of the regulator. Four-layer PCB with 2-ounce copper on the top and bottom side and thermal vias connecting the layers is recommended. Keep power traces wide and short to minimize losses and ringing. Do not connect AGND to PGND below the IC. Connect AGND pin to PGND at the output OR to the PGND plane. Figure 37. Recommended PCB Layout Figure 34. Synchronization Timing Diagram (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 15 FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability Physical Dimensions 2X TOP VIEW 2X SIDE VIEW SEATING PLANE RECOMMENDED LAND PATTERN ALL VALUES TYPICAL EXCEPT WHERE NOTED OPTIONAL LEAD DESIGN (LEADS# 1, 24 & 25 ONLY) SCALE: 1.5X BOTTOM VIEW A) DIMENSIONS ARE IN MILLIMETERS. B) DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) DESIGN BASED ON JEDEC MO-220 VARIATION WJHC E) TERMINALS ARE SYMMETRICAL AROUND THE X & Y AXIS EXCEPT WHERE DEPOPULATED. F) DRAWING FILENAME: MKT-MLP25AREV3 Figure 38. 5x6mm Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 www.fairchildsemi.com 17 www.fairchildsemi.com FAN21SV06 -- TinyBuckTM 6A, 24V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability (c) 2006 Fairchild Semiconductor Corporation FAN21SV06 Rev. 1.0.1 18 |
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